STM32F4
Technical notes tagged STM32F4.
STM32 USART Interrupt-Driven Communication — Register-Level Configuration on STM32F4
Complete register-level guide to STM32F4 USART interrupt-driven TX/RX: baud rate generation, data format, TXE/RXNE/TC interrupt management, overrun/framing error handling, ring buffer implementation, and a practical GPS module communication example.
STM32 SPI Master Full-Duplex — Register-Level Configuration on STM32F4
Complete register-level guide to configuring STM32 SPI in full-duplex master mode on STM32F4: clock polarity/phase, baud rate, data frame format, NSS management, and interrupt-driven data exchange with C code.
STM32 Flash Option Bytes:RDP Levels, BOR Configuration, Boot Modes, and OTP Programming at Register Level
STM32 flash option bytes: configure read protection (RDP Level 0/1/2), BOR threshold, boot mode, and one-time programmable (OTP) area at register level. Practical examples for STM32F4, L4, G4, and U5.
STM32 RTC Backup Domain:VBAT, Backup Registers, Tamper Detection, and Wake-Up from Low-Power Modes
STM32 RTC backup domain: configure VBAT-powered RTC calendar, backup registers, tamper detection with timestamp, and wake-up from STOP/STANDBY modes. Register-level examples for STM32F4, L4, G4, U5.
STM32 DAC with Timer Trigger + DMA:Generating Arbitrary Waveforms Without CPU Overhead
STM32 DAC with timer-triggered DMA: configure the DAC at register level, use TIM6 as update trigger, and stream arbitrary waveform samples via circular DMA without CPU intervention. Practical STM32F4/G4/L4 examples.
STM32 IWDG Watchdog:Silent Reset Prevention in Production Firmware
Master the STM32 Independent Watchdog (IWDG): LSI clock, prescaler, reload register, window option, debug freeze, proper feeding patterns, reset-cause detection, and a complete production-grade template for STM32F4/STM32U5.
STM32 RCC Clock Configuration at Register Level:HSI, HSE, PLL, and System Clock Switching on STM32F4
Configure the STM32F4 clock tree entirely through registers: HSI/HSE oscillator startup, PLL configuration (M/N/P/Q dividers), AHB/APB prescalers, and glitch-free system clock switching. Register-level walkthrough with a practical 168 MHz setup example.
STM32 SPI Master Mode at Register Level: Baud Rate, CPOL/CPHA, NSS, and DMA Transfers on STM32F4
A practical register-level guide to configuring the STM32F4 SPI peripheral in master mode: baud rate prescaler, clock polarity/phase, software NSS management, half-duplex bi-directional mode, CRC, and DMA-based full-duplex transfers with complete C code examples for STM32F401.
STM32 ADC Scan Sequence with DMA: Continuous Multi-Channel Acquisition on STM32F4
A practical guide to configuring the STM32F4 ADC in scan mode with continuous conversion and DMA: register-level setup, regular channel sequencing, injected groups, calibration, and a real multi-channel acquisition example for sensor data logging.
STM32 USART Interrupt-Driven Ring Buffer: Lock-Free RX/TX on STM32F4
A practical guide to implementing a lock-free ring buffer for USART interrupt-driven communication on STM32F4: register-level USART setup, circular buffer design with power-of-2 masking, RX/TX interrupt handlers, and a fully working echo/command parser.
STM32 I2C Master Mode at Register Level: SCL Timing, Start/Stop, and Multi-Byte Transfers
A practical STM32F4 firmware guide to I2C master mode at register level: SCL timing calculation through CCR/TRISE, start/stop generation, address transmission, multi-byte data transfer, NACK handling, and the anti-patterns I fix on client projects.