STM32
Technical notes tagged STM32.
STM32 CRC Peripheral: Hardware Checksum for Data Integrity, Bootloader Verification, and Communication
A practical register-level guide to the STM32 CRC calculation unit: polynomial configuration, data alignment, one-shot and streaming usage, bootloader integrity checks, and communication CRC.
STM32 USART Interrupt-Driven Communication — Register-Level Configuration on STM32F4
Complete register-level guide to STM32F4 USART interrupt-driven TX/RX: baud rate generation, data format, TXE/RXNE/TC interrupt management, overrun/framing error handling, ring buffer implementation, and a practical GPS module communication example.
STM32 SPI Master Full-Duplex — Register-Level Configuration on STM32F4
Complete register-level guide to configuring STM32 SPI in full-duplex master mode on STM32F4: clock polarity/phase, baud rate, data frame format, NSS management, and interrupt-driven data exchange with C code.
STM32 PVD (Programmable Voltage Detector):Replacing External Supervisor ICs with On-Chip Brownout Detection
STM32 Programmable Voltage Detector (PVD) at register level: threshold selection, interrupt and event mode, brownout detection without an external supervisor IC. Practical example on STM32G4 and STM32U5.
STM32 I2C Master Mode:Register-Level Configuration and Error Handling
STM32 I2C master mode at register level: timing calculation, transmit/receive sequence, NACK handling, arbitration lost, bus recovery, and a practical sensor-read example for G4, H7, and U5 series.
STM32 MPU Configuration:Protecting Memory Regions in Production Firmware
STM32 MPU (Memory Protection Unit) configuration at register and CMSIS level: set up region attributes, subregions, and privilege separation for production firmware on Cortex-M3/M4/M7/M33.
STM32 HardFault debugging — reading Cortex-M fault registers without a debugger
Practical guide to recovering HardFault root cause on STM32 by reading CFSR, HFSR, and stacked context from firmware — no JTAG/SWD needed.
STM32 Flash Option Bytes:RDP Levels, BOR Configuration, Boot Modes, and OTP Programming at Register Level
STM32 flash option bytes: configure read protection (RDP Level 0/1/2), BOR threshold, boot mode, and one-time programmable (OTP) area at register level. Practical examples for STM32F4, L4, G4, and U5.
STM32 RTC Backup Domain:VBAT, Backup Registers, Tamper Detection, and Wake-Up from Low-Power Modes
STM32 RTC backup domain: configure VBAT-powered RTC calendar, backup registers, tamper detection with timestamp, and wake-up from STOP/STANDBY modes. Register-level examples for STM32F4, L4, G4, U5.
STM32 DAC with Timer Trigger + DMA:Generating Arbitrary Waveforms Without CPU Overhead
STM32 DAC with timer-triggered DMA: configure the DAC at register level, use TIM6 as update trigger, and stream arbitrary waveform samples via circular DMA without CPU intervention. Practical STM32F4/G4/L4 examples.
STM32 FPU Configuration at Register Level:Enabling, Lazy Stacking, and Hard Fault Pitfalls
STM32 FPU configuration at register level on Cortex-M4 and M7: enabling the FPU via CPACR, lazy stacking, compiler ABI flags, and the most common hard fault causes. Practical guide for senior embedded engineers.
STM32 System Memory Bootloader:Flashing Firmware Without a Debugger
STM32 System Memory Bootloader: access the ROM bootloader via USART, I2C, SPI, CAN FD, and USB DFU. Practical guide to production programming, field updates, and brick recovery without a debugger.
STM32 Clock Security System (CSS):Detecting and Recovering from HSE Failure
STM32 Clock Security System (CSS): detect HSE failure at runtime, handle NMI, and implement a safe fallback strategy for production firmware.
STM32 IWDG Watchdog:Silent Reset Prevention in Production Firmware
Master the STM32 Independent Watchdog (IWDG): LSI clock, prescaler, reload register, window option, debug freeze, proper feeding patterns, reset-cause detection, and a complete production-grade template for STM32F4/STM32U5.
STM32H7 D-Cache Coherency:The DMA Pitfall Every Embedded Engineer Must Understand
Master STM32H7 data cache maintenance for DMA buffers: SCB_CleanDCache, SCB_InvalidateDCache, SCB_CleanInvalidateDCache, MPU memory type configuration, and a practical template to avoid stale-data corruption on Cortex-M7 peripherals.
STM32 Flash Dual Bank Mode:Enabling Bank Swap for Safe OTA Updates on G4, L4 and U5
Configure STM32 dual-bank flash mode: option byte programming for bank organization, bank swapping via FLASH_OPTCR, interrupt vector table relocation, and a complete safe OTA update architecture with fallback on STM32G4/L4/U5.
STM32 RCC Clock Configuration at Register Level:HSI, HSE, PLL, and System Clock Switching on STM32F4
Configure the STM32F4 clock tree entirely through registers: HSI/HSE oscillator startup, PLL configuration (M/N/P/Q dividers), AHB/APB prescalers, and glitch-free system clock switching. Register-level walkthrough with a practical 168 MHz setup example.
STM32 EXTI at Register Level:SYSCFG, GPIO Interrupt Mapping, and NVIC Wiring
Configure STM32 EXTI external interrupts without HAL: SYSCFG_EXTICR GPIO mapping, EXTI rising/falling edge triggers, interrupt mask, pending flag clearing, and NVIC integration. Register-level walkthrough on STM32F4 with a practical push-button example.
STM32 Advanced Timer PWM:Dead-Time Insertion and Complementary Outputs
Configure TIM1/TIM8 advanced-control timers for centre-aligned PWM with dead-time insertion and complementary CHxN outputs. Register-level walkthrough on STM32F4: BDTR, CCMR, CCER, ARR/CCR, break inputs, and a full half-bridge motor-control example.
STM32 SPI Master Mode at Register Level: Baud Rate, CPOL/CPHA, NSS, and DMA Transfers on STM32F4
A practical register-level guide to configuring the STM32F4 SPI peripheral in master mode: baud rate prescaler, clock polarity/phase, software NSS management, half-duplex bi-directional mode, CRC, and DMA-based full-duplex transfers with complete C code examples for STM32F401.
STM32 ADC Scan Sequence with DMA: Continuous Multi-Channel Acquisition on STM32F4
A practical guide to configuring the STM32F4 ADC in scan mode with continuous conversion and DMA: register-level setup, regular channel sequencing, injected groups, calibration, and a real multi-channel acquisition example for sensor data logging.
STM32 USART Interrupt-Driven Ring Buffer: Lock-Free RX/TX on STM32F4
A practical guide to implementing a lock-free ring buffer for USART interrupt-driven communication on STM32F4: register-level USART setup, circular buffer design with power-of-2 masking, RX/TX interrupt handlers, and a fully working echo/command parser.
STM32 I2C Master Mode at Register Level: SCL Timing, Start/Stop, and Multi-Byte Transfers
A practical STM32F4 firmware guide to I2C master mode at register level: SCL timing calculation through CCR/TRISE, start/stop generation, address transmission, multi-byte data transfer, NACK handling, and the anti-patterns I fix on client projects.
STM32 Flash Memory: Writing, Erasing, and Managing Persistent Data at Runtime
A practical guide to on-chip flash programming on STM32: unlock sequence, register-level write/erase, sector vs page architecture, option bytes, EEPROM emulation, and production-grade patterns for F4, G0, and U5 series.
STM32 Timer Input Capture: Measuring Frequency and Duty Cycle at Register Level
A practical STM32 firmware guide to timer input capture: single/dual-channel frequency and duty-cycle measurement, register-level configuration, overflow handling, and real-world pitfalls on STM32F4 and G4.
STM32 RCC Configuration: HSE, PLL, and Flash Latency from Registers
A practical walkthrough of STM32 RCC clock tree initialization from registers: HSE oscillator start, PLL configuration with N/M/P/Q dividers, flash wait-states, and the exact startup sequence to avoid hard faults.
STM32 NVIC Priority Grouping: Why Your Interrupt Preemption Is Not Working as Expected
A practical STM32 firmware guide to NVIC priority grouping, PRIGROUP, preempt vs subpriority, the AIRCR register, and how misconfiguration causes priority inversion in production.
STM32 DMA Circular Mode with Double Buffering: The Pattern That Prevents Data Loss
Practical STM32 DMA double-buffering guide: circular mode, half-transfer interrupts, cache coherence on Cortex-M7, DMA mux, UART/ADC examples, and the anti-patterns I fix on client projects.