Tag

Register-Level

Technical notes tagged Register-Level.

2026-07-04

STM32 USART Interrupt-Driven Communication — Register-Level Configuration on STM32F4

Complete register-level guide to STM32F4 USART interrupt-driven TX/RX: baud rate generation, data format, TXE/RXNE/TC interrupt management, overrun/framing error handling, ring buffer implementation, and a practical GPS module communication example.

2026-07-02

STM32 SPI Master Full-Duplex — Register-Level Configuration on STM32F4

Complete register-level guide to configuring STM32 SPI in full-duplex master mode on STM32F4: clock polarity/phase, baud rate, data frame format, NSS management, and interrupt-driven data exchange with C code.

2026-06-25

STM32 I2C Master Mode:Register-Level Configuration and Error Handling

STM32 I2C master mode at register level: timing calculation, transmit/receive sequence, NACK handling, arbitration lost, bus recovery, and a practical sensor-read example for G4, H7, and U5 series.

2026-06-12

STM32 RCC Clock Configuration at Register Level:HSI, HSE, PLL, and System Clock Switching on STM32F4

Configure the STM32F4 clock tree entirely through registers: HSI/HSE oscillator startup, PLL configuration (M/N/P/Q dividers), AHB/APB prescalers, and glitch-free system clock switching. Register-level walkthrough with a practical 168 MHz setup example.

2026-06-11

STM32 EXTI at Register Level:SYSCFG, GPIO Interrupt Mapping, and NVIC Wiring

Configure STM32 EXTI external interrupts without HAL: SYSCFG_EXTICR GPIO mapping, EXTI rising/falling edge triggers, interrupt mask, pending flag clearing, and NVIC integration. Register-level walkthrough on STM32F4 with a practical push-button example.

2026-06-10

STM32 Advanced Timer PWM:Dead-Time Insertion and Complementary Outputs

Configure TIM1/TIM8 advanced-control timers for centre-aligned PWM with dead-time insertion and complementary CHxN outputs. Register-level walkthrough on STM32F4: BDTR, CCMR, CCER, ARR/CCR, break inputs, and a full half-bridge motor-control example.

2026-06-07

STM32 SPI Master Mode at Register Level: Baud Rate, CPOL/CPHA, NSS, and DMA Transfers on STM32F4

A practical register-level guide to configuring the STM32F4 SPI peripheral in master mode: baud rate prescaler, clock polarity/phase, software NSS management, half-duplex bi-directional mode, CRC, and DMA-based full-duplex transfers with complete C code examples for STM32F401.