I2C

2026-06-25

STM32 I2C Master Mode:Register-Level Configuration and Error Handling

STM32 I2C master mode at register level: timing calculation, transmit/receive sequence, NACK handling, arbitration lost, bus recovery, and a practical sensor-read example for G4, H7, and U5 series.

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2026-06-03

STM32 I2C Master Mode at Register Level: SCL Timing, Start/Stop, and Multi-Byte Transfers

A practical STM32F4 firmware guide to I2C master mode at register level: SCL timing calculation through CCR/TRISE, start/stop generation, address transmission, multi-byte data transfer, NACK handling, and the anti-patterns I fix on client projects.

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2026-05-27

ESP-IDF 6.x I2C Master Driver: Migrating Without Hiding Bus Faults

A practical embedded firmware guide to the ESP-IDF I2C master bus/device driver, register reads, NACK handling, timeouts, and migration from legacy I2C code.

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