Tag
Cortex-M7
Technical notes tagged Cortex-M7.
2026-06-18
STM32 FPU Configuration at Register Level:Enabling, Lazy Stacking, and Hard Fault Pitfalls
STM32 FPU configuration at register level on Cortex-M4 and M7: enabling the FPU via CPACR, lazy stacking, compiler ABI flags, and the most common hard fault causes. Practical guide for senior embedded engineers.
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2026-06-14
STM32H7 D-Cache Coherency:The DMA Pitfall Every Embedded Engineer Must Understand
Master STM32H7 data cache maintenance for DMA buffers: SCB_CleanDCache, SCB_InvalidateDCache, SCB_CleanInvalidateDCache, MPU memory type configuration, and a practical template to avoid stale-data corruption on Cortex-M7 peripherals.
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